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NXP Semiconductors
12
I DD
(mA)
8
LPC11C12/C14
002aaf390
48 MHz (2)
36 MHz (2)
24 MHz (2)
4
12 MHz (1)
0
1.8
2.4
3.0
3.6
V DD (V)
Conditions: T amb = 25 ° C; active mode entered executing code while(1){} from flash; all
peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks
disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 6.
Active mode: Typical supply current I DD versus supply voltage V DD for different
system clock frequencies
12
I DD
(mA)
8
4
48 MHz (2)
36 MHz (2)
24 MHz (2)
12 MHz (1)
002aaf391
0
? 40
? 15
10
35
60 85
temperature ( ° C)
Conditions: V DD = 3.3 V; active mode entered executing code while(1){} from flash; all
peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks
disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 7.
Active mode: Typical supply current I DD versus temperature for different system
clock frequencies
LPC11C12_C14_0
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 00.05 — 23 April 2010
? NXP B.V. 2010. All rights reserved.
28 of 49
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